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FIFO BUFFER
RDS-TCB Tail Circuit Buffer
The RDS-TCB Tail-Circuit Buffer is designed to provide selectable
bi-directional buffering between two data circuits that are operating at
nominally the same clock rate and are capable of providing clocking as a DCE. In
such cases, the timing of the two circuits is not locked to the same timing
source, or may be allowed to deviate from a com-mon timing source for a length
of time. The RDS-TCB meets this need by pro-viding selectable amounts of
bi-directional memory from 1,024 bits up to 8,192 bits and supports synchronous
clock rates up to 2.048 Mbps.
RDS-SB Satellite Buffer
The RDS-SB is a device intended to provide a unidirectional 2.097
Mbit elastic data buffering (FIFO memory) function between two systems having
nominally equivalent clocking rates. The two systems may be either running
asynchronously, or may be traceable to a common timing source.
RDS-STB Selectable Transmit Buffer
The Selectable Transmit Buffer (RSD-STB) allows DCE to DTE
connections at data rates up to 10Mbps.
Allows the user to even the network delays between a terrestrial and satellite
network for transactions.
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